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october 1995 order number: 231256-004 82C55a chmos programmable peripheral interface y compatible with all intel and most other microprocessors y high speed, ``zero wait state'' operation with 8 mhz 8086/88 and 80186/188 y 24 programmable i/o pins y low power chmos y completely ttl compatible y control word read-back capability y direct bit set/reset capability y 2.5 ma dc drive capability on all i/o port outputs y available in 40-pin dip and 44-pin plcc y available in express e standard temperature range e extended temperature range the intel 82C55a is a high-performance, chmos version of the industry standard 8255a general purpose programmable i/o device which is designed for use with all intel and most other microprocessors. it provides 24 i/o pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. the 82C55a is pin compatible with the nmos 8255a and 8255a-5. in mode 0, each group of 12 i/o pins may be programmed in sets of 4 and 8 to be inputs or outputs. in mode 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. mode 2 is a strobed bi-directional bus configuration. the 82C55a is fabricated on intel's advanced chmos iii technology which provides low power consumption with performance equal to or greater than the equivalent nmos product. the 82C55a is available in 40-pin dip and 44-pin plastic leaded chip carrier (plcc) packages. 231256 1 figure 1. 82C55a block diagram 231256 31 231256 2 figure 2. 82C55a pinout diagrams are for pin reference only. package sizes are not to scale.
82C55a table 1. pin description symbol pin number type name and function dip plcc pa 30 14 25 i/o port a, pins 0 3: lower nibble of an 8-bit data output latch/ buffer and an 8-bit data input latch. rd 56i read control: this input is low during cpu read operations. cs 67i chip select: a low on this input enables the 82C55a to respond to rd and wr signals. rd and wr are ignored otherwise. gnd 7 8 system ground a 10 89 910 i address: these input signals, in conjunction rd and wr , control the selection of one of the three ports or the control word registers. a 1 a 0 rd wr cs input operation (read) 00010 port a - data bus 01010 port b - data bus 10010 port c - data bus 11010 control word - data bus output operation (write) 00100 data bus - port a 01100 data bus - port b 10100 data bus - port c 11100 data bus - control disable function xxxx1 data bu s-3- state x x 1 1 0 data bu s-3- state pc 74 10 13 11,13 15 i/o port c, pins 4 7: upper nibble of an 8-bit data output latch/ buffer and an 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. pc 03 1417 1619 i/o port c, pins 0 3: lower nibble of port c. pb 0-7 18 25 20 22, i/o port b, pins 0 7: an 8-bit data output latch/buffer and an 8- 24 28 bit data input buffer. v cc 26 29 system power: a 5v power supply. d 70 27 34 30 33, i/o data bus: bi-directional, tri-state data bus lines, connected to 35 38 system data bus. reset 35 39 i reset: a high on this input clears the control register and all ports are set to the input mode. wr 36 40 i write control: this input is low during cpu write operations. pa 74 3740 4144 i/o port a, pins 4 7: upper nibble of an 8-bit data output latch/ buffer and an 8-bit data input latch. nc 1, 12, no connect 23, 34 2
82C55a 82C55a functional description general the 82C55a is a programmable peripheral interface device designed for use in intel microcomputer sys- tems. its function is that of a general purpose i/o component to interface peripheral equipment to the microcomputer system bus. the functional configu- ration of the 82C55a is programmed by the system software so that normally no external logic is neces- sary to interface peripheral devices or structures. data bus buffer this 3-state bidirectional 8-bit buffer is used to inter- face the 82C55a to the system data bus. data is transmitted or received by the buffer upon execution of input or output instructions by the cpu. control words and status information are also transferred through the data bus buffer. read/write and control logic the function of this block is to manage all of the internal and external transfers of both data and control or status words. it accepts inputs from the cpu address and control busses and in turn, issues commands to both of the control groups. group a and group b controls the functional configuration of each port is pro- grammed by the systems software. in essence, the cpu ``outputs'' a control word to the 82C55a. the control word contains information such as ``mode'', ``bit set'', ``bit reset'', etc., that initializes the func- tional configuration of the 82C55a. each of the control blocks (group a and group b) accepts ``commands'' from the read/write control logic, receives ``control words'' from the internal data bus and issues the proper commands to its as- sociated ports. control grou p a - port a and port c upper (c7 c4) control group b - port b and port c lower (c3 c0) the control word register can be both written and read as shown in the address decode table in the pin descriptions. figure 6 shows the control word format for both read and write operations. when the control word is read, bit d7 will always be a logic ``1'', as this implies control word mode information. ports a, b, and c the 82C55a contains three 8-bit ports (a, b, and c). all can be configured in a wide variety of functional characteristics by the system software but each has its own special features or ``personality'' to further enhance the power and flexibility of the 82C55a. port a. one 8-bit data output latch/buffer and one 8-bit input latch buffer. both ``pull-up'' and ``pull- down'' bus hold devices are present on port a. port b. one 8-bit data input/output latch/buffer. only ``pull-up'' bus hold devices are present on port b. port c. one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports a and b. only ``pull-up'' bus hold devices are present on port c. see figure 4 for the bus-hold circuit configuration for port a, b, and c. 3
82C55a 231256 3 figure 3. 82C55a block diagram showing data bus buffer and read/write control logic functions * note: 231256 4 port pins loaded with more than 20 pf capacitance may not have their logic level guaranteed following a hardware reset. figure 4. port a, b, c, bus-hold configuration 4
82C55a 82C55a operational description mode selection there are three basic modes of operation that can be selected by the system software: mode 0 e basic input/output mode 1 e strobed input/output mode 2 e bi-directional bus when the reset input goes ``high'' all ports will be set to the input mode with all 24 port lines held at a logic ``one'' level by the internal bus hold devices (see figure 4 note). after the reset is removed the 82C55a can remain in the input mode with no addi- tional initialization required. this eliminates the need for pullup or pulldown devices in ``all cmos'' de- signs. during the execution of the system program, any of the other modes may be selected by using a single output instruction. this allows a single 82C55a to service a variety of peripheral devices with a simple software maintenance routine. the modes for port a and port b can be separately defined, while port c is divided into two portions as required by the port a and port b definitions. all of the output registers, including the status flip-flops, will be reset whenever the mode is changed. modes may be combined so that their functional definition can be ``tailored'' to almost any i/o structure. for instance; group b can be programmed in mode 0 to monitor simple switch closings or display computa- tional results, group a could be programmed in mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. 231256 5 figure 5. basic mode definitions and bus interface 231256 6 figure 6. mode definition format the mode definitions and possible mode combina- tions may seem confusing at first but after a cursory review of the complete device operation a simple, logical i/o approach will surface. the design of the 82C55a has taken into account things such as effi- cient pc board layout, control signal definition vs pc layout and complete functional flexibility to support almost any peripheral device with no external logic. such design represents the maximum use of the available pins. single bit set/reset feature any of the eight bits of port c can be set or reset using a single output instruction. this feature re- duces software requirements in control-based appli- cations. when port c is being used as status/control for port a or b, these bits can be set or reset by using the bit set/reset operation just as if they were data output ports. 5
82C55a 231256 7 figure 7. bit set/reset format interrupt control functions when the 82C55a is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the cpu. the interrupt request signals, generated from port c, can be inhibited or enabled by setting or resetting the associated inte flip-flop, using the bit set/reset function of port c. this function allows the programmer to disallow or allow a specific i/o device to interrupt the cpu with- out affecting any other device in the interrupt struc- ture. inte flip-flop definition: (bit-set)einte is seteinterrupt enable (bit-reset)einte is reseteinterrupt disable note: all mask flip-flops are automatically reset during mode selection and device reset. 6
82C55a operating modes mode 0 (basic input/output). this functional con- figuration provides simple input and output opera- tions for each of the three ports. no ``handshaking'' is required, data is simply written to or read from a specified port. mode 0 basic functional definitions: # two 8-bit ports and two 4-bit ports. # any port can be input or output. # outputs are latched. # inputs are not latched. # 16 different input/output configurations are pos- sible in this mode. mode 0 (basic input) 231256 8 mode 0 (basic output) 231256 9 7
82C55a mode 0 port definition a b group a group b d 4 d 3 d 1 d 0 port a port c y port b port c (upper) (lower) 0 0 0 0 output output 0 output output 0 0 0 1 output output 1 output input 0 0 1 0 output output 2 input output 0 0 1 1 output output 3 input input 0 1 0 0 output input 4 output output 0 1 0 1 output input 5 output input 0 1 1 0 output input 6 input output 0 1 1 1 output input 7 input input 1 0 0 0 input output 8 output output 1 0 0 1 input output 9 output input 1 0 1 0 input output 10 input output 1 0 1 1 input output 11 input input 1 1 0 0 input input 12 output output 1 1 0 1 input input 13 output input 1 1 1 0 input input 14 input output 1 1 1 1 input input 15 input input mode 0 configurations 231256 10 8
82C55a mode 0 configurations (continued) 231256 11 9
82C55a mode 0 configurations (continued) 231256 12 operating modes mode 1 (strobed input/output). this functional configuration provides a means for transferring i/o data to or from a specified port in conjunction with strobes or ``handshaking'' signals. in mode 1, port a and port b use the lines on port c to generate or accept these ``handshaking'' signals. mode 1 basic functional definitions: # two groups (group a and group b). # each group contains one 8-bit data port and one 4-bit control/data port. # the 8-bit data port can be either input or output both inputs and outputs are latched. # the 4-bit port is used for control and status of the 8-bit data port. 10
82C55a input control signal definition stb (strobe input). a ``low'' on this input loads data into the input latch. ibf (input buffer full f/f) a ``high'' on this output indicates that the data has been loaded into the input latch; in essence, an ac- knowledgement. ibf is set by stb input being low and is reset by the rising edge of the rd input. intr (interrupt request) a ``high'' on this output can be used to interrupt the cpu when an input device is requesting service. intr is set by the stb is a ``one'', ibf is a ``one'' and inte is a ``one''. it is reset by the falling edge of rd . this procedure allows an input device to re- quest service from the cpu by simply strobing its data into the port. inte a controlled by bit set/reset of pc 4 . inte b controlled by bit set/reset of pc 2 . 231256 13 figure 8. mode 1 input 231256 14 figure 9. mode 1 (strobed input) 11
82C55a output control signal definition obf (output buffer full f/f). the obf output will go ``low'' to indicate that the cpu has written data out to the specified port. the obf f/f will be set by the rising edge of the wr input and reset by ack input being low. ack (acknowledge input). a ``low'' on this input informs the 82C55a that the data from port a or port b has been accepted. in essence, a response from the peripheral device indicating that it has received the data output by the cpu. intr (interrupt request). a ``high'' on this output can be used to interrupt the cpu when an output device has accepted data transmitted by the cpu. intr is set when ack is a ``one'', obf is a ``one'' and inte is a ``one''. it is reset by the falling edge of wr . inte a controlled by bit set/reset of pc 6 . inte b controlled by bit set/reset of pc 2 . 231256 15 figure 10. mode 1 output 231256 16 figure 11. mode 1 (strobed output) 12
82C55a combinations of mode 1 port a and port b can be individually defined as input or output in mode 1 to support a wide variety of strobed i/o applications. 231256 17 figure 12. combinations of mode 1 operating modes mode 2 (strobed bidirectional bus i/o). this functional configuration provides a means for com- municating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus i/o). ``handshaking'' signals are provided to maintain proper bus flow discipline in a similar manner to mode 1. interrupt generation and enable/disable functions are also available. mode 2 basic functional definitions: # used in group a only . # one 8-bit, bi-directional bus port (port a) and a 5- bit control port (port c). # both inputs and outputs are latched. # the 5-bit control port (port c) is used for control and status for the 8-bit, bi-directional bus port (port a). bidirectional bus i/o control signal definition intr (interrupt request). a high on this output can be used to interrupt the cpu for input or output oper- ations. output operations obf (output buffer full). the obf output will go ``low'' to indicate that the cpu has written data out to port a. ack (acknowledge). a ``low'' on this input enables the tri-state output buffer of port a to send out the data. otherwise, the output buffer will be in the high impedance state. inte 1 (the inte flip-flop associated with obf ). controlled by bit set/reset of pc 6 . input operations stb (strobe input). a ``low'' on this input loads data into the input latch. ibf (input buffer full f/f). a ``high'' on this output indicates that data has been loaded into the input latch. inte 2 (the inte flip-flop associated with ibf). controlled by bit set/reset of pc 4 . 13
82C55a 231256 18 figure 13. mode control word 231256 19 figure 14. mode 2 231256 20 figure 15. mode 2 (bidirectional) note: any sequence where wr occurs before ack , and stb occurs before rd is permissible. (intr e ibf # mask # stb # rd a obf # mask # ack # wr ) 14
82C55a 231256 21 figure 16. mode (/4 combinations 15
82C55a mode definition summary mode 0 mode 1 mode 2 in out in out group a only pa 0 in out in out y pa 1 in out in out y pa 2 in out in out y pa 3 in out in out y pa 4 in out in out y pa 5 in out in out y pa 6 in out in out y pa 7 in out in out y pb 0 in out in out e pb 1 in out in out e pb 2 in out in out e pb 3 in out in out e mode 0 pb 4 in out in out e or mode 1 pb 5 in out in out e only pb 6 in out in out e pb 7 in out in out e pc 0 in out intr b intr b i/o pc 1 in out ibf b obf b i/o pc 2 in out stb b ack b i/o pc 3 in out intr a intr a intr a pc 4 in out stb a i/o stb a pc 5 in out ibf a i/o ibf a pc 6 in out i/o ack a ack a pc 7 in out i/o obf a obf a special mode combination considerations there are several combinations of modes possible. for any combination, some or all of the port c lines are used for control or status. the remaining bits are either inputs or outputs as defined by a ``set mode'' command. during a read of port c, the state of all the port c lines, except the ack and stb lines, will be placed on the data bus. in place of the ack and stb line states, flag status will appear on the data bus in the pc2, pc4, and pc6 bit positions as illustrated by figure 18. through a ``write port c'' command, only the port c pins programmed as outputs in a mode 0 group can be written. no other pins can be affected by a ``write port c'' command, nor can the interrupt enable flags be accessed. to write to any port c output pro- grammed as an output in a mode 1 group or to change an interrupt enable flag, the ``set/reset port c bit'' command must be used. with a ``set/reset port c bit'' command, any port c line programmed as an output (including intr, ibf and obf ) can be written, or an interrupt enable flag can be either set or reset. port c lines programmed as inputs, including ack and stb lines, associated with port c are not affected by a ``set/reset port c bit'' command. writing to the corresponding port c bit positions of the ack and stb lines with the ``set/reset port c bit'' command will affect the group a and group b interrupt enable flags, as illus- trated in figure 18. current drive capability any output on port a, b or c can sink or source 2.5 ma. this feature allows the 82C55a to directly drive darlington type drivers and high-voltage displays that require such sink or source current. 16
82C55a reading port c status in mode 0, port c transfers data to or from the pe- ripheral device. when the 82C55a is programmed to function in modes 1 or 2, port c generates or ac- cepts ``hand-shaking'' signals with the peripheral de- vice. reading the contents of port c allows the pro- grammer to test or verify the ``status'' of each pe- ripheral device and change the program flow ac- cordingly. there is no special instruction to read the status in- formation from port c. a normal read operation of port c is executed to perform this function. input configuration d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i/o i/o ibf a inte a intr a inte b ibf b intr b group a group b output configurations d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 obf a inte a i/o i/o intr a inte b obf b intr b group a group b figure 17a. mode 1 status word format d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 obf a inte 1 ibf a inte 2 intr a group a group b (defined by mode 0 or mode 1 selection) figure 17b. mode 2 status word format interrupt enable flag position alternate port c pin signal (mode) inte b pc2 ack b (output mode 1) or stb b (input mode 1) inte a2 pc4 stb a (input mode 1 or mode 2) inte a1 pc6 ack a (output mode 1 or mode 2 figure 18. interrupt enable flags in modes 1 and 2 17
82C55a absolute maximum ratings * ambient temperature under bias0 cto a 70 c storage temperature b 65 cto a 150 c supply voltage b 0.5 to a 8.0v operating voltage a 4v to a 7v voltage on any inputgnd b 2v to a 6.5v voltage on any output gnd b 0.5v to v cc a 0.5v power dissipation 1 watt notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics t a e 0 cto70 c, v cc ea 5v g 10%, gnd e 0v (t a eb 40 cto a 85 c for extended temperture) symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc v v ol output low voltage 0.4 v i ol e 2.5 ma v oh output high voltage 3.0 v i oh eb 2.5 ma v cc b 0.4 v i oh eb 100 m a i il input leakage current g 1 m av in e v cc to 0v (note 1) i ofl output float leakage current g 10 m av in e v cc to 0v (note 2) i dar darlington drive current g 2.5 (note 4) ma ports a, b, c r ext e 500 x v ext e 1.7v i phl port hold low leakage current a 50 a 300 m av out e 1.0v port a only i phh port hold high leakage current b 50 b 300 m av out e 3.0v ports a, b, c i phlo port hold low overdrive current b 350 m av out e 0.8v i phho port hold high overdrive current a 350 m av out e 3.0v i cc v cc supply current 10 ma (note 3) i ccsb v cc supply current-standby 10 m av cc e 5.5v v in e v cc or gnd port conditions if i/p e open/high o/p e open only with data bus e high/low cs e high reset e low pure inputs e low/high notes: 1. pins a 1 ,a 0 ,cs ,wr ,rd , reset. 2. data bus; ports b, c. 3. outputs open. 4. limit output current to 4.0 ma. 18
82C55a capacitance t a e 25 c, v cc e gnd e 0v symbol parameter min max units test conditions c in input capacitance 10 pf unmeasured plns returned to gnd c i/o i/o capacitance 20 pf f c e 1 mhz (5) note: 5. sampled not 100% tested. a.c. characteristics t a e 0 to 70 c, v cc ea 5v g 10%, gnd e 0v t a eb 40 cto a 85 c for extended temperature bus parameters read cycle symbol parameter 82C55a-2 units test min max conditions t ar address stable before rd v 0ns t ra address hold time after rd u 0ns t rr rd pulse width 150 ns t rd data delay from rd v 120 ns t df rd u to data floating 10 75 ns t rv recovery time between rd /wr 200 ns write cycle symbol parameter 82C55a-2 units test min max conditions t aw address stable before wr v 0ns t wa address hold time after wr u 20 ns port sa&b 20 ns port c t ww wr pulse width 100 ns t dw data setup time before wr u 100 ns t wd data hold time after wr u 30 ns port sa&b 30 ns port c 19
82C55a other timings symbol parameter 82C55a-2 units test min max conditions t wb wr e 1 to output 350 ns t lr peripheral data before rd 0ns t hr peripheral data after rd 0ns t ak ack pulse width 200 ns t st stb pulse width 100 ns t ps per. data before stb high 20 ns t ph per. data after stb high 50 ns t ad ack e 0 to output 175 ns t kd ack e 1 to output float 20 250 ns t wob wr e 1toobf e 0 150 ns t aob ack e 0toobf e 1 150 ns t sib stb e 0toibf e 1 150 ns t rib rd e 1toibf e 0 150 ns t rit rd e 0 to intr e 0 200 ns t sit stb e 1 to intr e 1 150 ns t ait ack e 1 to intr e 1 150 ns t wit wr e 0 to intr e 0 200 ns see note 1 t res reset pulse width 500 ns see note 2 note: 1. intr u may occur as early as wr v . 2. pulse width of initial reset pulse after power on must be at least 50 m sec. subsequent reset pulses may be 500 ns minimum. the output ports a, b, or c may glitch low during the reset pulse but all port pins will be held at a logic ``one'' level after the reset pulse. 20
82C55a waveforms mode 0 (basic input) 231256 22 mode 0 (basic output) 231256 23 21
82C55a waveforms (continued) mode 1 (strobed input) 231256 24 mode 1 (strobed output) 231256 25 22
82C55a waveforms (continued) mode 2 (bidirectional) 231256 26 note: any sequence where wr occurs before ack and stb occurs before rd is permissible. (intr e ibf # mask # stb # rd a obf # mask # ack # wr ) write timing 231256 27 read timing 231256 28 a.c. testing input, output waveform 231256 29 a.c. testing inputs are driven at 2.4v for a logic 1 and 0.45v for a logic 0 timing measurements are made at 2.0v for a logic 1 and 0.8 for a logic 0. a.c. testing load circuit 231256 30 * v ext is set at various voltages during testing to guarantee the specification. c l includes jig capacitance. 23

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